SH7014 datasheet(399/754 Pages) RENESAS

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12. Serial Communication Interface (SCI)

Rev.5.00 Sep. 27, 2007 Page 365 of 716

REJ09B0398-0500

07 8

15 0

7 8

15 0

Internal

base clock

Receive

data (RxD)

Synchronization

sampling timing

Data

sampling timing

8 clocks

16 clocks

Start bit

−7.5 clocks

+7.5 clocks

Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in the asynchronous mode can therefore be expressed as:

M = 0.5

−

− 0.5

− (L − 0.5)F −

(1 + F)

× 100 %

Legend:

M : Receive margin (

N : Ratio of clock frequency to bit rate (N = 16)

D : Clock duty cycle (D = 0

− 1.0)

L : Frame length (L = 9

− 12)

F : Absolute deviation of clock frequency

From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875

= 0.5, F = 0

M = (0.5

− 1/(2 × 16)) × 100%

= 46.875

This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30

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