SH7014 datasheet(400/754 Pages) RENESAS

400 / 754 page

12. Serial Communication Interface (SCI)

Rev.5.00 Sep. 27, 2007 Page 366 of 716

REJ09B0398-0500

12.5.7

Constraints on DMAC Use

• When using an external clock source for the synchronization clock, update the TDR with the

DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit

clock is input in the first four system clocks after the TDR is written, an error may occur

(figure 12.22).

• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full

interrupt (RXI) of the SCI as a start-up source.

SCK

TDRE

Note: During external clock operation, an error may occur if t is 4

φ or less.

Figure 12.22 Example of Clock Synchronous Transmission with DMAC

12.5.8

Cautions for Clock Synchronous External Clock Mode

• Set TE = RE = 1 only when the external clock SCK is 1.

• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed

from 0 to 1.

• When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the

RxD D7 bit SCK input, but it cannot be copied to RDR.

12.5.9

Caution for Clock Synchronous Internal Clock Mode

When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7

bit SCK output, but it cannot be copied to RDR.

SH7014 Datasheet(PDF) 400 Page - Renesas Technology Corp