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SH7014 Datasheet(PDF) 439 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 439 Page - Renesas Technology Corp |
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439 / 754 page ![]() 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Rev.5.00 Sep. 27, 2007 Page 405 of 716 REJ09B0398-0500 14.3 Interface with CPU Although A/D data register ADDRA to ADDRD are 16-bit registers, the bus width within the chip that integrates with the CPU is 8-bits. So, the lower byte data is read through the temporary register (TEMP). The upper byte data can be read directly. The procedure for reading data from ADDR is as follows: First, read the upper byte data from ADDR. At this time, the upper byte data is read directly into the CPU and the lower byte data is transferred to TEMP of the mid-speed A/D converter. Next, read the lower byte to read the TEMP contents into the CPU. When reading the ADDR in byte size, read the upper byte before the lower byte. Furthermore, it is possible to read only the upper byte, however, please note that contents are not guaranteed when reading only the lower byte. In this case, ADDR can be read from the upper-byte address with a word transfer instruction (such as MOV.W). Figure 14.2 shows the data flow when reading from ADDR. |
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