SH7014 datasheet(583/754 Pages) RENESAS

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20. RAM

Rev.5.00 Sep. 27, 2007 Page 549 of 716

REJ09B0398-0500

Section 20 RAM

20.1

Overview

The SH7014 and SH7016 have 3 kbytes of on-chip RAM, and the SH7017 has 4 kbytes. The on-

chip RAM is linked to the CPU and direct memory access controller (DMAC) with a 32-bit data

bus (figure 20.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The

DMAC can access 8 or 16 bit widths. On-chip RAM data can always be accessed in one state,

making the RAM ideal for use as a program area, stack area, or data area, which require high-

speed access. The contents of the on-chip RAM are held in both the sleep and standby modes.

Memory area 0 addresses H'FFFFF000 to H'FFFFFBFF (SH7014, SH7016) or H'FFFFF000 to

H'FFFFFFFF (SH7017) are allocated to the on-chip RAM.

The on-chip RAM is also used as cache memory. When the cache is used, 1 kbyte of on-chip

RAM is available in the SH7014 and SH7016, and 2 kbytes in the SH7017. See section 7, Cache

Memory, for details.

H'FFFFF000

H'FFFFF004

H'FFFFF001

H'FFFFF005

H'FFFFF002

H'FFFFF006

H'FFFFF003

H'FFFFF007

H'FFFFFBFC

H'FFFFFBFD

H'FFFFFBFE

H'FFFFFBFF

On-chip RAM

H'FFFFFFFC

H'FFFFFFFD

H'FFFFFFFE

H'FFFFFFFF

Internal data bus (32-bit)

Note: Operation is not guaranteed if addresses H'FFFFFC00 to H'FFFFFFFF

are accessed in the SH7014 or SH7016.

Figure 20.1 Block Diagram of RAM

SH7014 Datasheet(PDF) 583 Page - Renesas Technology Corp