SH7014 datasheet(586/754 Pages) RENESAS

586 / 754 page

21. Power-Down State

Rev.5.00 Sep. 27, 2007 Page 552 of 716

REJ09B0398-0500

Table 21.1

Power-Down State Conditions

State

Mode

Entering

Procedure

Clock CPU

On-Chip

Peripheral

Modules

CPU

Registers RAM

I/O

Ports

Canceling

Procedure

Sleep

Execute SLEEP

instruction with

SBY bit set to 0

in SBYCR

Run

Halt

Run

Held

• Interrupt

• DMAC

address error

• Power-on

reset

Stand-

Execute SLEEP

instruction with

SBY bit set to 1

in SBYCR

Halt

Halt*

Held

Held or

high

impe-

dance*

• NMI interrupt

• Power-on

reset

Legend:

SBYCR: standby control register

SBY:

standby bit

Notes: 1. Some bits within on-chip peripheral module registers are initialized by the standby

mode; some are not. Refer to table 21.3, Register States in the Standby Mode, in

section 21.4.1, Transition to Standby Mode. Also refer to the register descriptions for

each peripheral module.

2. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of

the SBYCR. Refer to section 21.2, Standby Control Register. For pin status other than

for the I/O port, refer to Appendix C, Pin Status.

21.1.2

Related Register

Table 21.2 shows the register used for power-down state control.

Table 21.2

Related Register

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Standby control register

SBYCR

R/W

H'1F

H'FFFF8614

8, 16, 32

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