SH7014 datasheet(588/754 Pages) RENESAS

588 / 754 page

21. Power-Down State

Rev.5.00 Sep. 27, 2007 Page 554 of 716

REJ09B0398-0500

21.3

Sleep Mode

21.3.1

Transition to Sleep Mode

Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the

program execution state to the sleep mode. Although the CPU halts immediately after executing

the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip

peripheral modules continue to run during the sleep mode.

21.3.2

Canceling Sleep Mode

Sleep mode is canceled by an interrupt, DMAC address error, or power-on reset.

Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt

exception processing is executed. The sleep mode is not canceled if the interrupt cannot be

accepted because its priority level is equal to or less than the mask level set in the CPU's status

module.

Cancellation by a DMAC Address Error: If a DMAC address error occurs, the sleep mode is

canceled and DMAC address error exception processing is executed.

Cancellation by a Power-On Reset: A power-on reset resulting from setting the

RES pin to low

level cancels the sleep mode.

21.4

Standby Mode

21.4.1

Transition to Standby Mode

To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.

The LSI moves from the program execution state to the standby mode. In the standby mode,

power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip

peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the

prescribed voltages are applied. The register contents of some on-chip peripheral modules are

initialized, but some are not (table 21.3). The I/O port status can be selected as held or high

impedance by the port high impedance bit (HIZ) of the SBYCR. For pin status other than for the

I/O port, refer to Appendix B, Pin Status.

SH7014 Datasheet(PDF) 588 Page - Renesas Technology Corp