SH7014 datasheet(589/754 Pages) RENESAS

589 / 754 page

21. Power-Down State

Rev.5.00 Sep. 27, 2007 Page 555 of 716

REJ09B0398-0500

Table 21.3

Module

Registers Initialized

Registers that

Retain Data

Registers with

Undefined Contents

Interrupt controller

(INTC)

⎯

All registers

⎯

Cache memory (CAC)

⎯

All registers

⎯

Bus state controller

(BSC)

⎯

All registers

⎯

Direct memory access

controller (DMAC)

• DMA channel control

registers 0, 1 (CHCR0,

CHCR1)

• DMA operation register

(DMAOR)

⎯

• DMA source

address registers

0, 1 (SAR0, SAR1)

• DMA destination

address registers

0, 1 (DAR0, DAR1)

• DMA transfer count

registers 0, 1

(DMATCR0,

DMATCR1)

Multifunction timer

pulse unit (MTU)

MTU associated registers

⎯

Watchdog timer

(WDT)

• Bits 7 to 5 (OVF, WT/

IT, TME)

of the timer control status

• Reset control/status register

(RSTCSR)

• Bits 2 to 0

(CKS2 to

CKS0) of the

TCSR

• Timer counter

(TCNT)

⎯

Serial communication

interface (SCI)

• Receive data register (RDR)

• Transmit data register (TDR)

• Serial mode register (SMR)

• Serial control register (SCR)

• Serial status register (SSR)

• Bit rate register (BBR)

⎯

A/D converter (A/D)

All registers

⎯

Compare match timer

(CMT)

All registers

⎯

Pin function controller

(PFC)

⎯

All registers

⎯

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