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7641 Datasheet(PDF) 184 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 184 Page - Renesas Technology Corp |
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184 / 385 page  Rev.2.00 Aug 28, 2006 page 53 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.4 UART 2.4.2 Related registers Fig. 2.4.2 Structure of UARTx (x = 1, 2) mode register UARTx mode register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) mode register (UxMOD : addresses 3016, 3816) b 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 0 UART clock prescaling select bits (PS) Parity select bit (PMD) Parity enable bit (PEN) Stop bit length select bit (STB) 0 : φ 1 : SCSGCLK output b2b1 0 0 : UART clock divided by 1 0 1 : UART clock divided by 8 1 0 : UART clock divided by 32 1 1 : UART clock divided by 256 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled 5 0 UART character length select bit (LE1, 0) 6 7 0 UART clock select bit (CLK) 3 b7b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not available |
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