7641 datasheet(182/385 Pages) RENESAS

182 / 385 page

Rev.2.00

Aug 28, 2006

page 51 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.3 Serial I/O

2.3.5 Notes on serial I/O

(1) Clock

When the external clock is selected as the transfer clock, its transfer clock needs to be controlled

by the external source because the serial I/O shift register will keep being shifted while transfer clock

is input even after transfer completion.

(2) Reception

When the external clock is selected as the transfer clock for reception, the receiving operation will

start owing to the shift clock input even if write operation to the serial I/O shift register (SIOSHT) is

not performed. The serial I/O interrupt request also occurs at completion of receiving. However, we

recommend to write dummy data in the serial I/O shift register. Because this will cause followings

and improve transfer reliability.

•Write to SIOSHT puts the SRDY pin to “L”. This enables shift clock output of an external device.

•Write to SIOSHT clears the internal serial I/O counter.

Note: Do not read the serial I/O shift register which is shifting. Because this will cause incorrect-data

read.

(3) STXD output

•When the internal clock is selected as the transfer clock, the STXD pin goes a high-impedance state

after transfer completion.

•When the external clock is selected as the transfer clock, the STXD pin does not go a high-

impedance state after transfer completion.

(4) SPI compatible mode

•When using the SPI compatible mode, set the SRDY select bit to “1” (SRDY signal output).

•When the external clock is selected in SPI compatible mode, the SRXD pin functions as a data

output pin and the STXD pin functions as a data input pin.

•Do not write to the serial I/O shift register (SIOSHT) during a transfer as slave when in SPI compatible

mode.

•Master operation of SPI compatible mode requires the timings:

-From write operation to the SIOSHT to SRDY pin put to “L”

Requires 2 cycles of internal clock

φ + 2 cycles of serial I/O synchronous clock + 35 ns

-From SRDY pin put to “L” to SCLK switch

Requires 35 ns

-From the last pulse of SCLK to SRDY pin put to “H”

Requires 35 ns.

7641 Datasheet(PDF) 182 Page - Renesas Technology Corp