7641 datasheet(186/385 Pages) RENESAS

186 / 385 page

Rev.2.00

Aug 28, 2006

page 55 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.4 UART

Fig. 2.4.4 Structure of UARTx (x = 1, 2) status register

UARTx status register

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) status register

(UxSTS : addresses 3216, 3A16)

Name

Functions

At reset R W

Transmit buffer empty flag

(TBE)

Parity error flag (PER)

Framing error flag (FER)

Receive buffer full flag

(RBF)

0 : Transmit shift in progress

1 : Transmit shift completed

0 : Buffer full

1 : Buffer empty

0 : Buffer empty

1 : Buffer full

0 : No error

1 : Parity error

0 : No error

1 : Framing error

Overrun error flag (OER)

0 : No error

1 : Overrun error

Summing error flag (SER)

0 : (PER) U (FER) U (OER) = 0

1 : (PER) U (FER) U (OER) = 1

Transmit complete flag

(TCM)

Nothing is arranged for this bit. This is a write disable bit. When this

bit is read out, the contents are “0”.

Fig. 2.4.5 Structure of UARTx (x = 1, 2) RTS control register

UARTx RTS control register

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) RTS control register

(UxRTSC : addresses 3616, 3E16)

Name

Functions

At reset R W

Fix these bits to “0”.

RTS assertion delay count

select bits (RTS)

b7b6b5b4

0 0 0 0 : No delay; Assertion immediately

0 0 0 1 : 8-bit term assertion at “H”

0 0 1 0 : 16-bit term assertion at “H”

0 0 1 1 : 24-bit term assertion at “H”

0 1 0 0 : 32-bit term assertion at “H”

0 1 0 1 : 40-bit term assertion at “H”

0 1 1 0 : 48-bit term assertion at “H”

0 1 1 1 : 56-bit term assertion at “H”

1 0 0 0 : 64-bit term assertion at “H”

1 0 0 1 : 72-bit term assertion at “H”

1 0 1 0 : 80-bit term assertion at “H”

1 0 1 1 : 88-bit term assertion at “H”

1 1 0 0 : 96-bit term assertion at “H”

1 1 0 1 : 104-bit term assertion at “H”

1 1 1 0 : 112-bit term assertion at “H”

1 1 1 1 : 120-bit term assertion at “H”

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