7641 datasheet(287/385 Pages) RENESAS

287 / 385 page

Rev.2.00

Aug 28, 2006

page 8 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.1 Electrical characteristics

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

AB15–AB8 delay time

AB15–AB8 valid time

AB7–AB0 delay time

AB7–AB0 valid time

WR delay time

WR valid time

RD delay time

RD valid time

SYNCOUT delay time

SYNCOUT valid time

DMAOUT delay time

DMAOUT valid time

RDY setup time

RDY hold time

HOLD setup time

HOLD hold time

HOLD “L” delay time

HOLD “H” delay time

Data bus setup time

Data bus hold time

Data bus delay time

Data bus valid time (Note 1)

EDMA delay time

EDMA valid time

WR pulse width

RD pulse width

AB15–AB8 valid time before WR

AB7–AB0 valid time before WR

AB15–AB8 valid time after WR

AB7–AB0 valid time after WR

AB15–AB8 valid time before RD

AB7–AB0 valid time before RD

AB15–AB8 valid time after RD

AB7–AB0 valid time after RD

RDY setup time before WR

RDY hold time after WR

RDY setup time before RD

RDY hold time after RD

Data bus setup time before RD

Data bus hold time after RD

Data bus delay time before WR

Data bus valid time after WR (Note 1)

EDMA delay time after WR

EDMA valid time after RD

USB output rise time, CL = 50 pF

USB output fall time, CL = 50 pF

tC(

φ)

tWH(

φ)

tWL(

φ)

td(

φ -AH)

tv(

φ -AH)

td(

φ -AL)

tv(

φ -AL)

td(

φ -WR)

tv(

φ -WR)

td(

φ -RD)

tv(

φ -RD)

td(

φ -SYNC)

tv(

φ -SYNC)

td(

φ -DMA)

tv(

φ -DMA)

tsu(RDY-

φ)

th(

φ -RDY)

tsu(HOLD-

φ)

th(

φ -HOLD)

td(

φ -HLDAL)

td(

φ -HLDAH)

tsu(DB-

φ)

th(

φ -DB)

td(

φ -DB)

tV(

φ -DB)

td(

φ -EDMA)

tv(

φ -EDMA)

tWL(WR) (Note 2)

tWL(RD) (Note 2)

td(AH-WR)

td(AL-WR)

tv(WR-AH)

tv(WR-AL)

td(AH-RD)

td(AL-RD)

tv(RD-AH)

tv(RD-AL)

tsu(RDY-WR)

th(WR-RDY)

tsu(RDY-RD)

th(RD-RDY)

tsu(DB-RD)

th(RD-DB)

td(WR-DB)

tv(WR-DB)

tv(WR-EDMA)

tv(RD-EDMA)

tr(D+), tr(D-)

tf(D+), tf(D-)

Limits

Parameter

Min.

83.33

0.5•tc(

φ) – 5

0.5•tc(

φ) – 5

0.5•tc(

φ) – 5

0.5•tc(

φ) – 5

0.5•tc(

φ) – 28

0.5•tc(

φ) – 30

0.5•tc(

φ) – 28

0.5•tc(

φ) – 30

Typ.

Max.

Symbol

Unit

In Vcc = 5 V

Table 3.1.8

Timing requirements and switching characteristics in memory expansion and

microprocessor modes

(Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)

7641 Datasheet(PDF) 287 Page - Renesas Technology Corp

7641 Datasheet(HTML) 287 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL