R8C13 datasheet(75/224 Pages) RENESAS

75 / 224 page

Rev.1.20

Jan 27, 2006

page 64 of 205

REJ09B0111-0120

R8C/13 Group

Timer C control register 0

SymbolAddressAfter reset

TCC0009A16

0016

Bit name

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : f1

0 1 : f8

1 0 : f32

1 1 : fRING-fast

TCC04

TCC02

TCC01

TCC00

TCC03

Timer C control bit

Timer C count source select

bit(1)

0 : Count stop

1 : Count start

TCC07

b2 b1

0 0 : Rising edge

0 1 : Falling edge

1 0 : Both edges

1 1 : Avoid this setting

b4 b3

(b6-b5)

INT3 interrupt and capture

polarity select bit(1, 2)

INT3 interrupt/capture input

switching bit(1, 2)

0 : INT3

1 : fRING128

NOTES:

1. Change this bit when TCC00 bit is set to “0” (count stop).

2. The IR bit in the INT3IC may be set to “1” (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten.

Refer to the paragraph 19.2.5 “Changing Interrupt Factir” in the Usage Notes Reference Book.

Reserved bit

Set to "0"

Figure 10.14 TCC0 Register and TCC1 Register

Timer C control register 1

SymbolAddressAfter reset

TCC1009B16

0016

Bit name

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

TCC11

TCC10

b1 b0

INT3 input filter select bit(1)

Timer C counter reload

select bit(2, 3)

TCC12

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

0: No reload (free-run)

1: Set TC register to “000016” at

compare 1 match

Compare 0/Capture select

bit

TCC13

0: Capture

(input capture mode)(2)

1: Compare 0 output

(output compare mode)

Compare 0 output mode

select bit(3)

TCC14

0 0: CMP output remains unchanged

even when compare 0 matched

0 1: CMP output is reversed when

compare 0 signal is matched

1 0: CMP output is set to low when

compare 0 signal is matched

1 1: CMP output is set to high when

compare 0 signal is matched

b5 b4

Compare 1 output mode

select bit(3)

TCC16

0 0: CMP output remains unchanged

even when compare 1 matched

0 1: CMP output is reversed when

compare 1 signal is matched

1 0: CMP output is set to low when

compare 1 signal is matched

1 1: CMP output is set to high when

compare 1 signal is matched

b7 b6

TCC15

TCC17

NOTES:

1. Input is recognized only when the same value from INT3 pin is sampled three times in succession.

2. Modify the TCC13 bit when the TCC00 bit in the TCC0 register is set to “0”(count stops)

3. Set the TCC12, TCC14 to TCC17 bits to “0” when the TCC13 bit is set to “0”(input capture mode).

______

10.2 INT Interrupt

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