SH7713 datasheet(351/904 Pages) RENESAS

351 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 311 of 860

REJ09B0288-0150

Section 11 On-Chip Oscillation Circuits

11.1

Overview

The oscillator consists of a clock pulse generator (CPG) block and a watchdog timer (WDT)

block.

The CPG generates clocks supplied to this LSI and controls the power-down modes.

The WDT is a single-channel timer that counts the clock settling time and is used when clearing

standby mode and temporary standbys, such as frequency changes. It can also be used as an

ordinary watchdog timer or interval timer.

11.1.1

Features

The CPG has the following features:

• Seven clock modes: Selection of seven clock modes according to the frequency range to be

used and direct connection of crystal resonator or external clock input.

• Three clocks generated independently: An internal clock (Iφ) for the CPU and cache; a

peripheral clock (P

φ) for the peripheral modules; and a bus clock (Bφ = CKIO) for the external

bus interface.

• Frequency change function: Internal and peripheral clock frequencies can be changed

independently using the PLL circuit and divider circuit within the CPG. Frequencies are

changed by software using frequency control register (FRQCR) settings.

• Power-down mode control: The clock can be stopped for sleep mode and standby mode and

specific modules can be stopped using the module standby function.

The WDT has the following features:

• Can be used to ensure the clock settling time:

Use the WDT to cancel standby mode and the temporary standbys which occur when the clock

frequency is changed.

• Can switch between watchdog timer mode and interval timer mode.

• Generates internal resets in watchdog timer mode:

Internal resets occur after counter overflow.

Selection of power-on reset or manual reset.

SH7713 Datasheet(PDF) 351 Page - Renesas Technology Corp