SH7713 datasheet(354/904 Pages) RENESAS

354 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 314 of 860

REJ09B0288-0150

The clock pulse generator blocks function as follows:

1. PLL Circuit 1: PLL circuit 1 doubles, triples, or leaves unchanged the input clock frequency

from the CKIO terminal. The multiplication rate is set by the frequency control register. When

this is done, the phase of the rising edge of the internal clock is controlled so that it will

synchronize with the phase of the rising edge of the CKIO pin.

2. PLL Circuit 2: PLL circuit 2 doubles, quadruples, or leaves unchanged the input clock

frequency from the crystal oscillator or EXTAL pin. The multiplication ratio is fixed by the

clock operating modes. The clock operating modes is set by pins MD0, MD1, and MD2. See

table 11.2 for more information on clock operating modes.

3. Crystal Oscillator: This oscillator is used when a crystal resonator is connected to the XTAL

and EXTAL pins. This crystal oscillator operates according to the clock operating mode

setting.

4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal or

peripheral clock. The operating frequency of the internal clock (I

φ) can be 1, 1/2, or 1/3 times

the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the

CKIO pin. The operating frequency of the peripheral clock (P

φ) can be 1/2, 1/3, 1/4, or 1/6

times the output frequency of PLL circuit 1 within 8.34 MHz

≤ Pφ ≤ 33.34 MHz. The division

ratio is set in the frequency control register.

5. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock

frequency using the MD pins and the frequency control register.

6. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator

and other modules during clock switching or in sleep or standby mode.

7. Frequency Control Register: The frequency control register has control bits assigned for the

following functions: clock output/non-output from the CKIO pin, the frequency multiplication

ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral

clock.

8. Standby Control Register: The standby control register has bits for controlling the power-down

modes. See section 10, Power-Down Modes, for more information.

SH7713 Datasheet(PDF) 354 Page - Renesas Technology Corp