SH7713 datasheet(361/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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361 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 321 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

STC1

STC0

R/W

Frequency Multiplication Ratio of PLL Circuit 1

00:

× 1 time

01:

× 2 times

10:

× 3 times

11: Reserved (setting prohibited)



Reserved

These bits are always read as 0. The write value

should always be 0.

IFC1

IFC0

R/W

Internal Clock Frequency Division Ratio

These bits specify the frequency division ratio of the

internal clock (I

φ) with respect to the output frequency

of PLL circuit 1.

00:

× 1 time

01:

× 1/2 time

10:

× 1/3 time

11: Reserved (setting prohibited)



Reserved

This bit is always read as 0. The write value should

always be 0.

PFC2

PFC1

PFC0

R/W

Peripheral Clock Frequency Division Ratio

These bits specify the division ratio of the peripheral

clock (P

φ) frequency with respect to the output

frequency of PLL circuit 1.

001:

× 1/2 time

010:

× 1/3 time

011:

× 1/4 time

100:

× 1/6 time

Other than above: Reserved (setting prohibited)

SH7713 Datasheet(PDF) 361 Page - Renesas Technology Corp

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