SH7713 datasheet(364/904 Pages) RENESAS

364 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 324 of 860

REJ09B0288-0150

11.7

The WDT has the following two registers that select the clock, switch the timer mode, and

perform other functions. For details on register addresses and register access size, refer to section

23, List of Registers.

• Watchdog timer counter (WTCNT)

• Watchdog timer control/status register (WTCSR)

11.7.1

Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable counter. WTCNT increments on the selected clock. When

an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time

mode. WTCNT is initialized to H'00 only by a power-on reset through the

RESETP pin. Use a

word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read WTCNT.

Note:

WTCNT differs from other registers in that it is more difficult to write to. See section

11.7.3, Notes on Register Access, for details.

11.7.2

Watchdog Timer Control/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the

count, bits to select the timer mode, and overflow flags.

WTCSR is initialized to H'00 only by a power-on reset through the

RESETP pin. When a WDT

overflow causes an internal reset, WTCSR retains its value. When used to count the clock settling

time for canceling a standby, it retains its value after counter overflow.

Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read

WTCSR.

Note:

WTCSR differs from other registers in that it is more difficult to write to. See section

11.7.3, Notes on Register Access, for details.

SH7713 Datasheet(PDF) 364 Page - Renesas Technology Corp