SH7713 datasheet(366/904 Pages) RENESAS

366 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 326 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select the clock to be used for the WTCNT

count from the eight types obtainable by dividing the

peripheral clock. The overflow period in the table is

the value when the peripheral clock (P

φ) is 15 MHz.

Clock

Overflow Period

Select

Division Ratio

(when P =15MHz)

000

17 s

001

1/4

68 s

010

1/16

273 s

011

1/32

546 s

100

1/64

1.09 ms

101

1/256

4.36 ms

110

1/1024

17.48 ms

111

1/4096

69.91 ms

Note:

If bits CKS2 to CKS0 are modified when the

WDT is running, the up-count may not be

performed correctly. Ensure that these bits

are modified only when the WDT is not

running.

11.7.3

Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are

more difficult to write to than other registers. The procedure for writing to these registers are given

below.

Writing to WTCNT and WTCSR: These registers must be written by a word transfer

instruction. They cannot be written by a byte or longword transfer instruction.

When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,

as shown in figure 11.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the

lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or

WTCSR.

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