SH7713 datasheet(368/904 Pages) RENESAS

368 / 904 page

Section 11 On-Chip Oscillation Circuits

Rev.1.50 Aug. 30, 2006 Page 328 of 860

REJ09B0288-0150

11.8.2

Changing Frequency

To change the frequency used by the PLL, use the WDT. When changing the frequency only by

switching the divider, do not use the WDT.

1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit

is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. When the frequency control register (FRQCR) is written, the processor stop temporarily. The

WDT starts counting.

4. When the WDT count overflows, the CPG resumes supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set at this time.

5. The counter stops at the values H'00.

6. Before changing the WTCNT after the execution of the frequency change instruction, always

confirm that the value of the WTCNT is H'00 by reading the WTCNT.

11.8.3

Using Watchdog Timer Mode

1. Set the WT/

IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count

clock in the CKS2 to CKS0 bits, and set the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.

3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent

the counter from overflowing.

4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the

type of reset specified by the RSTS bit. The counter then resumes counting.

11.8.4

Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of

the counter. This enables interrupts to be generated at set periods.

1. Clear the WT/

IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and

set the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.

3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval

timer interrupt request is sent to INTC. The counter then resumes counting.

SH7713 Datasheet(PDF) 368 Page - Renesas Technology Corp