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SH7713 Datasheet(PDF) 359 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 359 Page - Renesas Technology Corp |
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359 / 904 page ![]() Section 11 On-Chip Oscillation Circuits Rev.1.50 Aug. 30, 2006 Page 319 of 860 REJ09B0288-0150 Mode FRQCR Value PLL Circuit 1 PLL Circuit 2 Clock Ratio* (I:B:P) Frequency Range of Input Clock and Crystal Resonator Frequency Range of CKIO Pin 1103 On (x2) Off 2:1:1/2 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 1104 On (x2) Off 2:1:1/3 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz 7 1204 On (x3) Off 3:1:1/2 33.34 MHz to 66.67 MHz 33.34 MHz to 66.67 MHz Notes: * The input clock is 1. Maximum frequency: I φ = 200.00 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz 1. Use the CKIO frequency within 33.34 MHz ≤ CKIO ≤ 66.67 MHz. 2. The input to divider 1 is the output of PLL circuit 1. 3. Use the internal clock frequency within 33.34 MHz ≤ Iφ ≤ 200.00 MHz. The internal clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and the division ratio selected by the IFC bit in FRQCR. Do not set the internal clock frequency lower than the CKIO pin frequency. 4. Use the peripheral clock frequency within 8.34 MHz ≤ Pφ ≤ 33.34 MHz. The peripheral clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and the division ratio selected by the PFC bit in FRQCR. Do not set the peripheral clock frequency higher than the frequency of the CKIO pin. 5. × 1, × 2, or × 3 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, or × 1/3 can be selected as the division ratio of an internal clock. × 1/2, × 1/3, × 1/4, or × 1/6 can be selected as the division ratio of a peripheral clock. Set the rate in FRQCR. 6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. Use the output frequency under 200.00 MHz. |
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