SH7713 datasheet(390/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 350 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should always

be 0.

BSZ1

BSZ0

R/W

Data Bus Size

Specify the data bus sizes of spaces.

00: Reserved (setting prohibited)

01: 8-bit size

10: 16-bit size

11: 32-bit size

Notes:

1. The data bus width for area 0 is specified by

the external pin. The BSZ1 and BSZ0 bit

settings in CS0BCR are ignored.

2. If area 5 or area 6 is specified as PCMCIA

space, the bus width can be specified as either

8 bits or 16 bits.

3. If area 2 or area 3 is specified as SDRAM

space, the bus width can be specified as either

16 bits or 32 bits.

8 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

Notes: 1. CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at a

power-on reset.

2. The burst ROM (clock synchronous) must be accessed as a cacheable space.

SH7713 Datasheet(PDF) 390 Page - Renesas Technology Corp

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