SH7713 datasheet(422/904 Pages) RENESAS

422 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 382 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

RRC2

RRC1

RRC0

R/W

Refresh Count

Specify the number of continuous refresh cycles, when the

refresh request occurs after the coincidence of the values

of the refresh timer counter (RTCNT) and the refresh time

constant register (RTCOR). These bits can make the

period of occurrence of refresh long.

000: Once

001: Twice

010: 4 times

011: 6 times

100: 8 times

101: Reserved (setting prohibited)

110: Reserved (setting prohibited)

111: Reserved (setting prohibited)

12.4.6

Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in

RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to

0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must

be H’A55A to cancel write protection.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

7 to 0



All 0

R/W

8-bit Counter

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