SH7713 datasheet(424/904 Pages) RENESAS

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 384 of 860

REJ09B0288-0150

12.5

Operation

12.5.1

Endian/Access Size and Data Alignment

This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the

byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte

data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low

level on power-on reset, the endian will become big endian and when MD5 pin is high level on

power-on reset, the endian will become little endian.

Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-

selection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data

bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed

in accordance with the data bus width of the device and endian. This also means that when

longword data is read from a byte-width device, the read operation must be done four times. In

this LSI, data alignment and conversion of data length is performed automatically between the

respective interfaces.

Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit.

Table 12.6

32-Bit External Device/Big Endian Access and Data Alignment

Data Bus

Strobe Signals

Operation

D31 to

D24

D23 to

D16

D15 to

D7 to D0

WE3(BE3),

DQMUU

WE2(BE2),

DQMUL

WE1(BE1),

DQMLU

WE0(BE0),

DQMLL

Byte access

at 0

Data

7 to 0



Assert



Byte access

at 1



Data

7 to 0



Assert



Byte access

at 2



Data

7 to 0



Assert



Byte access

at 3



Data

7 to 0



Assert

Word

access at 0

Data

15 to 8

Data

7 to 0



Assert



Word

access at 2



Data

15 to 8

Data

7 to 0



Assert

Longword

access at 0

Data

31 to 24

Data

23 to 16

Data

15 to 8

Data

7 to 0

Assert

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