SH7713 datasheet(514/904 Pages) RENESAS

514 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 474 of 860

REJ09B0288-0150

Transfer requests from the various modules are specified by the MID and RID as shown in table

13.2.

Table 13.2

DMARS Setting

Peripheral

Module

Setting Value for One

Channel (MID + RID)

MID

RID

Function

H'21

B'01

Transmit

SCIF0

H'22

B'001000

B'10

Receive

H'29

B'01

Transmit

SCIF1

H'2A

B'001010

B'10

Receive

H'51

B'01

Transmit

SIOF0

H'52

B'010100

B'10

Receive

H'55

B'01

Transmit

SIOF1

H'56

B'010101

B'10

Receive

13.4

Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the

predetermined channel priority order; when the transfer end conditions are satisfied, it ends the

transfer. Transfers can be requested in three modes: auto request, external request, and on-chip

peripheral module request. In the bus mode, the burst mode or the cycle steal mode can be

selected.

13.4.1

DMA Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA

transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation

data according to the following procedure:

1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)

2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of

data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins

automatically when the DE bit and DME bit are set to 1. The DMATCR value will be

decremented for each transfer. The actual transfer flows vary by address mode and bus mode.

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