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SH7713 Datasheet(PDF) 515 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 515 Page - Renesas Technology Corp |
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515 / 904 page ![]() Section 13 Direct Memory Access Controller (DMAC) Rev.1.50 Aug. 30, 2006 Page 475 of 860 REJ09B0288-0150 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. |
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