SH7713 datasheet(519/904 Pages) RENESAS

519 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 479 of 860

REJ09B0288-0150

the SCIF0's receive data register. These conditions also apply to the SCIF1, SIOF0, and SIOF1.

Depending on the on-chip peripheral module, the number of receive FIFO triggers can be set as a

transfer request. If the receive FIFO trigger condition is not satisfied, data may be remained in the

receive FIFO. Therefore, data needs to be read upon completion of the DMA transfer.

Table 13.6

Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits

CHCR

DMARS

RS[3:0]

MID

RID

DMA Transfer

Request

Source

DMA Transfer

Request Signal

Source

Destination

Bus

Mode

SCIF0

transmitter

TXI (transmit FIFO data

empty interrupt)

Any

SCFTDR_0

Cycle

steal

001000

SCIF0

receiver

RXI (receive FIFO data

full interrupt)

SCFRDR_0

Any

Cycle

steal

SCIF1

transmitter

TXI (transmit FIFO data

empty interrupt)

Any

SCFTDR_1

Cycle

steal

001010

SCIF1

receiver

RXI (receive FIFO data

full interrupt)

SCFRDR_1

Any

Cycle

steal

SIOF0

transmitter

TXI (transmit FIFO data

empty interrupt)

Any

SITDR_0

Cycle

steal

010100

SIOF0

receiver

RXI (receive FIFO data

full interrupt)

SIOF0/

SIRDR_0

Any

Cycle

steal

SIOF1

transmitter

TXI (transmit FIFO data

empty interrupt)

Any

SITDR_1

Cycle

steal

1000

010101

SIOF1

receiver

RXI (receive FIFO data

full interrupt)

SIOF1/

SIRDR_1

Any

Cycle

steal

13.4.3

Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it selects a

channel according to a predetermined priority order. The two modes (fixed mode and round-robin

mode) can be selected using bits PR0 and PR1 in DMAOR.

Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two

kinds of fixed modes as follows:

Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5

Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5

These are selected by the PR1 and the PR0 bits in DMAOR.

SH7713 Datasheet(PDF) 519 Page - Renesas Technology Corp

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