SH7713 datasheet(523/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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523 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 483 of 860

REJ09B0288-0150

Data buffer

Memory

Transfer source

module

Transfer destination

module

Memory

Transfer source

module

Transfer destination

module

SAR

DAR

Data buffer

SAR

DAR

The SAR value is an address, data is read from the transfer source module,

and the data is temporarily stored in the DMAC.

First bus cycle

Second bus cycle

The DAR value is an address and the value stored in the data buffer in the

DMAC is written to the transfer destination module.

DMAC

Figure 13.5 Data Flow in Dual Address Mode

Auto request, external request, and on-chip peripheral module request are available for the

transfer request. DACK can be output in read cycle or write cycle in dual address mode. The

AM bit of the channel control register (CHCR) can specify whether the DACK is output in

read cycle or write cycle.

Figure 13.6 shows an example of DMA transfer timing in dual address mode.

SH7713 Datasheet(PDF) 523 Page - Renesas Technology Corp