SH7713 datasheet(524/904 Pages) RENESAS

524 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 484 of 860

REJ09B0288-0150

CKIO

A25 to A0

Note: In transfer between external memories, with DACK output in the read cycle,

DACK output timing is the same as that of

CSn.

D31 to D0

WEn

DACKn

(Active-Low)

CSn

Transfer source

address

Transfer destination

address

Data read cycle

Data write cycle

(1st cycle)

(2nd cycle)

Figure 13.6 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary

memory, Destination: Ordinary memory)

2. Single Address Mode

In single address mode, either the transfer source or transfer destination external device is

accessed (selected) by means of the DACK signal, and the other device is accessed by address.

In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the

external devices by outputting the DACK transfer request acknowledge signal to it, and at the

same time outputting an address to the other device involved in the transfer. For example, in

the case of transfer between external memory and an external device with DACK shown in

figure 13.7, when the external device outputs data to the data bus, that data is written to the

external memory in the same bus cycle.

SH7713 Datasheet(PDF) 524 Page - Renesas Technology Corp