SH7713 datasheet(526/904 Pages) RENESAS

526 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 486 of 860

REJ09B0288-0150

Address output to external memory space

Select signal to external memory space

Data output from external device with DACK

DACK signal (active-low) to external device with DACK

Write strobe signal to external memory space

Address output to external memory space

Data output from external memory space

DACK signal (active-low) to external device with DACK

Read strobe signal to external memory space

(a) External device with DACK

→ external memory space (ordinary memory)

(b) External memory space (ordinary memory)

→ external device with DACK

CKIO

A25 to A0

D31 to D0

DACKn

CSn

CKIO

A25 to A0

D31 to D0

DACKn

CSn

Figure 13.8 Example of DMA Transfer Timing in Single Address Mode

Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the

channel control register (CHCR).

• Cycle-Steal Mode

In the cycle-steal mode, the bus mastership is given to another bus master after a one-transfer-

unit (byte, word, long-word, or 16 bytes unit) DMA transfer. When another transfer request

occurs, the bus masterships are obtained from the other bus master and a transfer is performed

for one transfer unit. When that transfer ends, the bus mastership is passed to the other bus

master. This is repeated until the transfer end conditions are satisfied.

In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer

request source, transfer source, and transfer destination.

Figure 13.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer

conditions shown in the figure are:

1. Dual address mode

2. DREQ low level detection

SH7713 Datasheet(PDF) 526 Page - Renesas Technology Corp