SH7713 datasheet(522/904 Pages) RENESAS

522 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 482 of 860

REJ09B0288-0150

13.4.4

DMA Transfer Types

DMA transfer has two types; single address mode transfer and dual address mode transfer, They

depend on the number of bus cycles of access to source and destination. A data transfer timing

depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the

transfers shown in table 13.7.

Table 13.7

Supported DMA Transfers

Destination

Source

External

Device with

DACK

External

Memory

Memory-

Mapped

External

Device

On-Chip

Peripheral

Module

X/Y Memory

External device with DACK

Not

available

Single

Not

available

Not available

External memory

Single

Dual

Memory-mapped external

device

Single

Dual

On-chip peripheral module

Not

available

Dual

X/Y memory

Not

available

Dual

Notes: 1. Dual: Dual address mode

2. Single: Single address mode

3. 16-byte transfer is not available for on-chip peripheral modules.

Address Modes:

1. Dual Address Mode

In the dual address mode, both the transfer source and destination are accessed (selected) by an

address. The source and destination can be located externally or internally.

DMA transfer requires two bus cycles because data is read from the transfer source in a data

read cycle and written to the transfer destination in a data write cycle. At this time, transfer

data is temporarily stored in the DMAC. In the transfer between external memories as shown

in figure 13.5, data is read to the DMAC from one external memory in a data read cycle, and

then that data is written to the other external memory in a write cycle.

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