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SH7713 Datasheet(PDF) 703 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 703 Page - Renesas Technology Corp

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Section 18 Ethernet Controller (EtherC)
Rev.1.50 Aug. 30, 2006 Page 663 of 860
REJ09B0288-0150
MII Register Access Procedure: The program accesses MII registers via the PHY interface
register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data
read, bus release, and independent bus release. Figure 18.6 shows the MII register access timing.
The timing will differ depending on the PHY-LSI type.
MDC
(1)
(1) (2)
(3)
MDO
(2)
(3)
Write to PHY interface
register
1-bit data write timing
relationship
MMD = 1
MDO = write data
MDC = 0
MMD = 1
MDO = write data
MDC = 1
Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 0
Write to PHY interface
register
Figure 18.6 (1) 1-Bit Data Write Flowchart



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