SH7713 datasheet(702/904 Pages) RENESAS

702 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 662 of 860

REJ09B0288-0150

18.4.4

Accessing MII Registers

MII registers in the PHY-LSI are accessed via this LSI’s PHY interface register (PIR). Connection

is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.

MII Management Frame Format: The format of an MII management frame is shown in figure

18.5. To access an MII register, a management frame is implemented by the program in

accordance with the procedures shown in MII Register Access Procedure.

Access Type

MII Management Frame

Item

Number of bits

Read

Write

PRE

1..1

PHYAD

00001

REGAD

RRRRR

DATA

D..D

IDLE

PRE:

ST:

OP:

PHYAD:

REGAD:

TA:

DATA:

IDLE:

[Legend]

32 consecutive 1s

Write of 01 indicating start of frame

Write of code indicating access type

Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).

This bit changes depending on the PHY-LSI address.

Write of 0001 if the register address is 1 (sequential write starting with the MSB).

This bit changes depending on the PHY-LSI register address.

Time for switching data transmission source on MII interface

(a) Write: 10 written

(b) Read: Bus release (notation: Z0) performed

16-bit data. Sequential write or read from MSB

(a) Write: 16-bit data write

(b) Read: 16-bit data read

Wait time until next MII management format input

(a) Write: Independent bus release (notation: X) performed

(b) Read: Bus already released in TA; control unnecessary

Figure 18.5 MII Management Frame Format

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