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SH7713 Datasheet(PDF) 699 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 699 Page - Renesas Technology Corp

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Section 18 Ethernet Controller (EtherC)
Rev.1.50 Aug. 30, 2006 Page 659 of 860
REJ09B0288-0150
Illegal carrier
detection
Start of frame
reception
Wait for SFD
reception
Data
reception
CRC
reception
Destination address
reception
Preamble
detection
Reception
halted
Reset
Error
notification*
RE set
Legend
SFD: Start frame delimiter
Note: The error frame also transmits data to the buffer.
End of
reception
Receivce error
detection
Receivce error
detection
Error
detection
Promiscuous and other
station destination address
RE reset
Normal reception
Idle
RX-DV negation
SFD
reception
Own destination address
or broadcast
or multicast
or promiscuous
Figure 18.3 EtherC Receiver State Transmissions
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
starts receive processing. Discards a frame with an invalid pattern.
3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast
or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
4. Following data reception from the MII, the receiver carries out a CRC check. The result is
indicated as a status bit in the descriptor after the frame data has been written to memory.
Reports an error status in the case of an abnormality.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.



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