SH7713 datasheet(695/904 Pages) RENESAS

695 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 655 of 860

REJ09B0288-0150

18.3.23

Transmit Frame Counter Register (Normal and Error Transmission) (TXALCR)

TXALCR is a 32-bit counter indicating the number of frames successfully transmitted and frames

transmitted with error in MAC. When the value in this register reaches H'FFFFFFFF, the count is

halted. The counter value is cleared to 0 by a read to this register. This register cannot be written.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 TC031 to

TC000

All 0

Transmit Frame Counter Bit

These bits indicate the number of frames successfully

transmitted and frames transmitted with error.

18.3.24

Receive Frame Counter Register (Normal Reception Only) (RXNLCR)

RXNLCR is a 32-bit counter indicating the number of frames successfully received in MAC.

When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is

cleared to 0 by a read to this register. This register cannot be written.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 NRC031 to

NRC000

All 0

Receive Frame Counter Bit

These bits indicate the number of frames successfully

received.

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