SH7713 datasheet(694/904 Pages) RENESAS

694 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 654 of 860

REJ09B0288-0150

18.3.21

TSU Counter Reset Register (TSU_CTRST)

TSU_CTRST clears the transmit and receive frame counters to 0.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 9



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CTRST

R/W

TSU Counter Reset

When 1 is written to this bit, the values of registers

TXNCR, TXALCR, RXNLCR, and RXALCR, are cleared

to 0. Writing 0 does not affect this bit. These bits are

always read as 0.

7 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

18.3.22

Transmit Frame Counter Register (Normal Transmission Only) (TXNLCR)

TXNLCR is a 32-bit counter indicating the number of frames successfully transmitted in MAC.

When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is

cleared to 0 by a read to this register. This register cannot be written.

Bit

Bit Name

Initial Value

R/W

Description

31 to 0 NTC031 to

NTC000

All 0

Transmit Frame Counter Bit

These bits indicate the number of frames

successfully transmitted.

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