SH7713 datasheet(696/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 656 of 860

REJ09B0288-0150

18.3.25

Receive Frame Counter Register (Normal and Error Reception) (RXALCR)

RXALCR is a 32-bit counter indicating the number of frames successfully received and frames

received with error in MAC. When the value in this register reaches H'FFFFFFFF, the count is

halted. The counter value is cleared to 0 by a read to this register. This register cannot be written.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 RC031 to

RC000

All 0

Receive Frame Counter Bit

These bits indicate the number of frames successfully

received and frames received with error.

18.4

Operation

The following outlines the operations of the Ethernet controller (EtherC).

18.4.1

Transmission

The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is

a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines

by PHY-LSI. Figure 18.2 shows the status change of the Ether-C transmitter.

SH7713 Datasheet(PDF) 696 Page - Renesas Technology Corp