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SH7713 Datasheet(PDF) 697 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 697 Page - Renesas Technology Corp

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Section 18 Ethernet Controller (EtherC)
Rev.1.50 Aug. 30, 2006 Page 657 of 860
REJ09B0288-0150
FDPX
FDPX
HDPX
HDPX
Collision
Collision
Collision*2
Collision*2
Error
Error
Error
Normal transmission
Notes:
1. Transmission retry processing includes both jam transmission that depends on collision
detection and the adjustment of transmission intervals based on the back-off algorithm.
2. Transmission is retried only when data of 512 bits or less (including the preamble and
SFD)is transmitted. When a collision is detected during the transmission of data greater
than 512 bits, only jam is transmitted and transmission based on the back-off algorithm
is not retried.
Legend
FDPX: Full-duplex
HDPX: Half-duplex
Error
notification
Transmission
halted
Start of transmission
(preamble transmission)
Carrier
detection
Carrier
detection
SFD
transmission
CRC
transmission
Data
transmission
Carrier
detection
Failure of 15
retransfer attempts
or collision
after 512-bit time
Retransfer
processing*1
Error detection
Retransfer
initiation
Carrier
non-detection
Carrier
non-detection
Carrier
detection
Idle
TE set
TE reset
Reset
Figure 18.2 EtherC Transmitter State Transitions
1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state.
2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble
after a transmission delay equivalent to the frame interval time. If full-duplex transfer is



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