SH7713 datasheet(693/904 Pages) RENESAS

693 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 653 of 860

REJ09B0288-0150

18.3.19

Multicast Address Frame Receive Counter Register (MAFCR)

MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast

address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter

value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 MAFC31 to

MAFC0

All 0

R/W

Multicast Address Frame Count

These bits indicate the count of multicast frames

received.

18.3.20

IPG Register (IPGR)

IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting

and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to

section 18.4.6, Operation by IPG Setting.)

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

4 to 0

IPG4 to

IPG0

′13

R/W

Inter Packet Gap

Sets the IPG value every 4-bit time.

′00: 20-bit time

′01: 24-bit time

′13: 96-bit time (Default)

′1F: 144-bit time

SH7713 Datasheet(PDF) 693 Page - Renesas Technology Corp

SH7713 Datasheet(HTML) 693 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL