SH7713 datasheet(689/904 Pages) RENESAS

689 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 649 of 860

REJ09B0288-0150

18.3.9

PHY Status Register (PSR)

PSR is a read-only register that can read interface signals from the PHY-LSI.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

LMON

LNKSTA Pin Status

The Link status can be read by connecting the Link

signal output from the PHY-LSI to the LNKSTA pin. For

the polarity, refer to the PHY-LSI specifications to be

connected.

18.3.10

Transmit Retry Over Counter Register (TROCR)

TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted

in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed,

TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is

halted. The counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 TROC31 to

TROC0

All 0

R/W

Transmit Retry Over Count

These bits indicate the number of frames that were

unable to be transmitted in 16 transmission attempts

including the retransfer.

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