SH7713 datasheet(686/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 646 of 860

REJ09B0288-0150

18.3.5

PHY Interface Register (PIR)

PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI registers

via the MII.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

MDI

Undefined

MII Management Data-In

Indicates the level of the MDIO pin.

MDO

R/W

MII Management Data-Out

Outputs the value set to this bit from the MDIO pin,

when the MMD bit is 1.

MMD

R/W

MII Management Mode

Specifies the data read/write direction with respect to

the MII.

0: Read direction is indicated

1: Write direction is indicated

MDC

R/W

MII Management Data Clock

Outputs the value set to this bit from the MDC pin

and supplies the MII with the management data

clock. For the method of accessing the MII registers,

see section 18.4.4, Accessing MII Registers.

SH7713 Datasheet(PDF) 686 Page - Renesas Technology Corp

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