SH7713 datasheet(684/904 Pages) RENESAS

684 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 644 of 860

REJ09B0288-0150

18.3.3

EtherC Status Register (ECSR)

ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can

be notified to the CPU by interrupts. When 1 is written to the LCHNG, MPD, and ICD, the

corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate

interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.

The interrupts generated due to this status register are indicated in ECI bit in EESR of the E-

DMAC derived.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

LCHNG

R/W

Link Signal Change

Indicates that the LNKSTA signal input from the PHY-

LSI has changed from high to low or low to high.

To check the current Link state, refer to the LMON bit in

the PHY status register (PSR).

0: Change in the LNKSTA signal has not been detected

1: Change in the LNKSTA signal has been detected

(high to low or low to high)

MPD

R/W

Magic Packet Detection

Indicates that a Magic Packet has been detected on the

line.

0: Magic Packet has not been detected

1: Magic Packet has been detected

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