SH7713 datasheet(681/904 Pages) RENESAS

681 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 641 of 860

REJ09B0288-0150

18.3.2

EtherC Mode Register (ECMR)

ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet

controller. The settings in this register are normally made in the initialization process following a

reset.

The operating mode setting must not be changed while the transmitting and receiving functions

are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states

by means of the SWR bit in EDMR before making settings again.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 13



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PRCEF

R/W

CRC Error Frame Reception Enable

0: A receive frame including a CRC error is received

as a frame with an error.

1: A receive frame including a CRC error is received

as a frame without an error.

When this bit is cleared to 0, the CRC error is

reflected in EESR of the E-DMAC and the status of

the receive descriptor. When this bit is set to 1, a

frame is received as a normal frame.



Reserved

These bits are always read as 0. The write value

should always be 0.

MPDE

R/W

Magic Packet Detection Enable

Enables or disables Magic Packet detection by

hardware to allow activation from the Ethernet.

0: Magic Packet detection is not enabled

1: Magic Packet detection is enabled



Reserved

These bits are always read as 0. The write value

should always be 0.

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