SH7713 datasheet(680/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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680 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 640 of 860

REJ09B0288-0150

18.3.1

Software Reset Register (ARSTR)

ARSTR resets all modules (EtherC and E-DMAC) related to the Ethernet. By writing 1 to the

ARST bit in ARSTR, a software reset is issued to all modules related to the Ethernet (for 64 cycles

at external bus clock B

φ). The ARST bit is always read as 0. While a software reset is issued,

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

ARST

R/W

Software Reset

When written with 1, a software reset is issued to all

modules related to the Ethernet (for 64 cycles at

external bus clock B

φ).

Writing 0 does not affect this bit. This bit is always read

as 0.

While a software reset is issued, register access to all

modules related to the Ethernet is prohibited. The

following registers are not initialized by a software

reset.

TXNLCR, TXALCR, RXNLCR, RXALCR

SH7713 Datasheet(PDF) 680 Page - Renesas Technology Corp