SH7713 datasheet(677/904 Pages) RENESAS

677 / 904 page

Section 18 Ethernet Controller (EtherC)

ISFETH01B_000020020900

Rev.1.50 Aug. 30, 2006 Page 637 of 860

REJ09B0288-0150

Section 18 Ethernet Controller (EtherC)

This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3

MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI)

complying with this standard enables the Ethernet controller (EtherC) to perform transmission and

reception of Ethernet/IEEE802.3 frames. The LSI has one MAC layer interface port which can be

made to perform transmission and reception independently. The Ethernet controller is connected

to the Ethernet Direct Memory Access Controller (E-DMAC) for Ethernet controller inside the

LSI, and carries out high-speed data transfer to and from the memory.

Figure 18.1 shows a configuration of the EtherC.

18.1

Features

• Transmission and reception of Ethernet/IEEE802.3 frames

• Supports 10/100 Mbps receive/transfer

• Supports full-duplex and half-duplex modes

• Conforms to IEEE802.3u standard MII (Media Independent Interface)

• Magic Packet detection and Wake-On-LAN (WOL) signal output

E-DMAC

Receive

controller

Transmit

controller

MII

Command status

interface

Ether C

MAC

PHY

E-DMAC Interface

Figure 18.1 Configuration of EtherC

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