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SH7713 Datasheet(PDF) 675 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 675 Page - Renesas Technology Corp

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Section 17 Serial I/O with FIFO (SIOF)
Rev.1.50 Aug. 30, 2006 Page 635 of 860
REJ09B0288-0150
17.5
Usage Notes
Note the following when using the SIOF.
1. Using the transmit function in slave mode
If transmission is enabled when data has already been written to the transmit FIFO, one or two
of the first data bytes may be lost.
Therefore, data should not be written to the transmit FIFO before enabling transmission.
2. Using control data transmission/reception consecutively on control data interface (secondary
FS position)
The TCRDY value may become 1 before transmit control data is sent, and if the next control
data is written to the control data register at this point, the control data waiting to be sent will
be overwritten and erased.
At this time, also, the control sequence is disrupted and the SIOF switches around the primary
FS and secondary FS, with the result that transmission/reception of data and control data can
no longer be performed normally.
The control data register should therefore be written to after transmit control data has been
sent.
Example:
Check RCRDY, and write to the control data register when RCRDY is 1.
After transmit control data has been written to, it is essential to read the receive control register
(SIRCR) and clear RCRDY.
3. DMA transfer
Do not use 16-byte DMA transfer. (See section 13.4.4, DMA Transfer Types.)
4. Access from the CPU
When performing access from the CPU, do not access the SIOF's transmit/receive FIFO
consecutively, but instead insert an access to somewhere else between SIOF transmit/receive
FIFO accesses.
5. Transmit/receive FIFO underflow
If the transmit/receive FIFO underflows during a transmit/receive operation, control of the
SIOF's transmit/receive FIFO may fail and data may be lost.
To prevent this, either set a watermark so that an underflow does not occur, or execute a
transmit reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated.
6. Transmit/receive reset execution
When using the SIOF again after a transmit/receive operation ends, or after erroneous
operation occurs, first execute a transmit reset (TXRST) or receive reset (RXRST).



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