SH7713 datasheet(678/904 Pages) RENESAS

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Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 638 of 860

REJ09B0288-0150

18.2

Input/Output Pins

Table 18.1 lists the pin configuration of the EtherC.

Table 18.1

Pin Configuration

Name

Abbreviation I/O

Function

Transmit clock

TX-CLK0*

TX-EN, ETXD3 to ETXD0, TX-ER timing reference

signal

Receive clock

RX-CLK0*

RX-DV, ERXD3 to ERXD0, RX-ER timing reference

signal

Transmit enable

TX-EN0*

Indicates that transmit data is ready on ETXD3 to

ETXD0

Transmit data

ETXD03 to

ETXD00*

4-bit transmit data

Transmit error

TX-ER0*

Notifies PHY_LSI of error during transmission

Receive data valid

RX-DV0*

Indicates that valid receive data is on ERXD3 to

ERXD0

Receive data

ERXD03 to

ERXD00*

4-bit receive data

Receive error

RX-ER0*

Identifies error state occurred during data reception

Carrier detection

CRS0*

Carrier detection signal

Collision detection

COL0*

Collision detection signal

Management data

clock

MDC0*

Reference clock signal for information transfer via

MDIO

Management data

I/O

MDIO0*

I/O

Bidirectional signal for exchange of management

information between this LSI and PHY

Link status

LNKSTA0

Inputs link status from PHY

General-purpose

external output

EXOUT0

Signal indicating value of register-bit (ECMR.ELB)

Wake-On-LAN

WOL0

Signal indicating reception of Magic Packet

Bus release request

ARBUSY*2

Signal indicating bus release request when the

threshold value set for the data volume in the receive

FIFO has been exceeded

Notes: 1. MII signal conforming to IEEE802.3u

2. Refer to section 19, Ethernet Controller Direct Memory Access Controller (E-DMAC)

and section 19.2.18, Overflow Alert FIFO Threshold Register (FCFTR), and section

19.3.5, Receive FIFO Overflow Alert Signal (

ARBUSY).

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