SH7713 datasheet(679/904 Pages) RENESAS

679 / 904 page

Section 18 Ethernet Controller (EtherC)

Rev.1.50 Aug. 30, 2006 Page 639 of 860

REJ09B0288-0150

18.3

The EtherC has the following registers. For details on addresses and access sizes of registers, see

section 23, List of Registers.

Reset Register:

• Software reset register (ARSTR)

MAC Layer Interface Control Registers:

• EtherC mode register (ECMR)

• EtherC status register (ECSR)

• EtherC interrupt permission register (ECSIPR)

• PHY interface register (PIR)

• MAC address high register (MAHR)

• MAC address low register (MALR)

• Receive frame length register (RFLR)

• PHY status register (PSR)

• Transmit retry over counter register (TROCR)

• Delayed collision detect counter register (CDCR)

• Lost carrier counter register (LCCR)

• Carrier not detect counter register (CNDCR)

• CRC error frame receive counter register (CEFCR)

• Frame receive error counter register (FRECR)

• Too-short frame receive counter register (TSFRCR)

• Too-long frame receive counter register (TLFRCR)

• Residual-bit frame receive counter register (RFCR)

• Multicast address frame receive counter register (MAFCR)

• IPG register (IPGR)

TSU Control Registers:

• TSU counter reset register (TSU_CTRST)

• Transmit frame counter register (normal transmission only) (TXNLCR)

• Transmit frame counter register (normal and error transmission) (TXALCR)

• Receive frame counter register (normal reception only) (RXNLCR)

• Receive frame counter register (normal and error reception) (RXALCR)

SH7713 Datasheet(PDF) 679 Page - Renesas Technology Corp