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SH7713 Datasheet(PDF) 673 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 673 Page - Renesas Technology Corp

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Section 17 Serial I/O with FIFO (SIOF)
Rev.1.50 Aug. 30, 2006 Page 633 of 860
REJ09B0288-0150
SCK_SIO
RXD_SIO
TXD_SIO
SIOFSYNC
TRMD = 01,
TDLE = 1,
RDLE = 1,
CD0E = 0,
REDG = 1,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0001,
CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length: 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0011,
CD1A3 to CD1A0 = 0000
Lch.DATA
Rch.DATA
Lch.DATA
Rch.DATA
Slot No.0
Slot No.1
Slot No.2
Slot No.3
Setting:
1 frame
No bit delay
Figure 17.17 Transmission and Reception Timings (16-Bit Stereo Data (2))
16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for left
channel data, slot No.2 used for right channel data, slot No.1 used for control channel 0 data, slot
No.3 used for control channel 1 data, frame length = 128 bits
SCK_SIO
RXD_SIO
TXD_SIO
SIOFSYNC
TRMD = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
REDG = 0,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0001,
FL = 1110 (frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0010,
CD1A3 to CD1A0 = 0011
Lch.DATA
Rch.DATA
Control
ch.1
Slot No.0
Slot No.1
Slot No.2
Slot No.3
Slot No.4
Slot No.5
Slot No.6
Slot No.7
Setting:
1 frame
1 bit delay
Control
ch.0
Figure 17.18 Transmission and Reception Timings (16-Bit Stereo Data (3))
16-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, request for
secondary FS, slot No.0 used for left channel data, slot No.0 used for control channel 0 data, frame
length = 128 bits



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