SH7713 datasheet(669/904 Pages) RENESAS

669 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 629 of 860

REJ09B0288-0150

Table 17.11 SIOF Interrupt Sources

No.

Classification

Bit Name

Function name

Description

Transmission

(TXI)

TDREQ

Transmit data transfer

request

The number of transmit FIFO data

is equal to or less than the specified

value by transmit operation.

Reception (RXI) RDREQ

Receive data transfer

request

The receive FIFO stores data of

specified value or more.

TCRDY

Transmit control data

ready

The transmit control data register is

ready to be written.

RCRDY

Receive control data

ready

The receive control data register

stores valid data.

TFEMP

Transmit FIFO empty The transmit FIFO is empty.

Control (CCI)

RFFUL

Receive FIFO full

The receive FIFO is full.

TFUDR

Transmit FIFO

underrun

Serial data transmission timing has

arrived while the transmit FIFO is

empty.

TFOVR

Transmit FIFO

overrun

Write to the transmit FIFO is

performed while the transmit FIFO

is full.

RFOVR

Receive FIFO

overrun

Serial data is received while the

receive FIFO is full.

RFUDR

Receive FIFO

underrun

The receive FIFO is read while the

receive FIFO is empty.

Error (ERI)

FSERR

Frame

synchronization error

A synchronous signal is input

before the specified bit time has

been passed (in slave mode).

Whether an interrupt is issued or not as the result of an interrupt source is determined by the

SIIER settings. If an interrupt source is set to 1, and the corresponding bit in SIIER is set to 1, the

SIOF issues each interrupt.

Transmit/Receive Interrupt Flag: Transmit and receive interrupts are sent to the INTC or

DMAC by this interrupt flag based on the values of bits TDREQ and RDREQ in SISTR.

Table17.12 shows the setting condition of the transmit/receive interrupt flag.

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