SH7713 datasheet(667/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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667 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 627 of 860

REJ09B0288-0150

Start

Yes

End

No.

Set SIMDR, SISCR, SITDAR,

SIRDAR, SICDAR, and SIFCTR

Set RXE bit in SICTR register to 1

RDREQ=1?

Transfer

ended?

Clear RXE bit in SICTR to 0

Set operating mode, serial clock,

slot positions for transmit/receive

data, slot position for control data,

and the upper limit value of FIFO

request

Time Chart

SIOF Settings

SIOF Operation

Submit reception request

according to the limit

value of receive FIFO

Reception

End reception

Read receive data

Set to disable reception

Read SIRDR

Store receive data from RXD_SIO

in SIRDR synchronously with SIOFSYNC

Set to enable reception

Enable reception when the

frame synchronous signal is

input

Figure 17.12 Example of Reception Operation in Slave Mode

Transmission/Reception Reset: The SIOF can separately reset the transmission and reception

units by setting the following bits to 1.

• Transmission reset: TXRST bit in SICTR

• Reception reset: RXRST bit in SICTR

SH7713 Datasheet(PDF) 667 Page - Renesas Technology Corp

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