SH7713 datasheet(664/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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664 / 904 page

Section 17 Serial I/O with FIFO (SIOF)

Rev.1.50 Aug. 30, 2006 Page 624 of 860

REJ09B0288-0150

Start

Yes

End

No.

Set SIMDR, SISCR, SITDAR,

SIRDAR, SICDAR, and SIFCTR

Set SCKE bit in SICTR to 1

Start SCK_SIO clock transmission

Set FSE bit in SICTR to 1

Set TXE bit in SICTR to 1

TDREQ=1?

Set SITDR

Output SITDR contents from TXD_SIO

synchronously with SIOFSYNC

Transfer

ended?

Clear TXE bit in SICTR to 0

Set operating mode, serial clock,

slot positions for transmit/receive

data, slot position for control data,

and the upper limit value of FIFO

request

Set operation start for baud rate

generator

Set the start for frame

synchronous signal

Transmit frame

synchronous signal

Submit transmission

request

Set to enable transmission

Set transmit data

Set to disable transmission

Output serial clock

Transmit

End transmission

Time Chart

SIOF Settings

SIOF Operation

Figure 17.9 Example of Transmission Operation in Master Mode

Reception in Master Mode: Figure 17.10 shows an example of settings and operation for master

mode reception.

SH7713 Datasheet(PDF) 664 Page - Renesas Technology Corp

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